| MikeB said: The Cell has cache memory as well. However the local memory stores are fully dedicated to each SPE processor and although this memory operates as fast as cache memory it's very different in usage, allowing them to operate independently (on one hardware thread and any number of software threads). |
This is starting to get into doublespeak again. My intent was just to clarify that there is a cache on Xenon that the cores can work with locally, so let's move on.
Actually, your quote about cache-friendly algorithms is exactly what I was talking about. Since you have to explicitly begin each DMA transfer, it basically forces you to think in terms of using the cache. You can still think in these terms on a symmetric system, but you don't have to in every place in your code, just the most important chunks. That's why it's a double-edged sword.
