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I don't get it at all. If we are talking about 512 stream processors with 4 FLOPS/clock cycle at 2 GHz, so it should be 4 TFLOPS instead of 3 as mentioned on the article.
I'm assuming TMUs are staying at 8 per array, so we have 128 now, and ROPs have been doubled from GT200's 32 up to 64...