Squilliam said:
I think people are forgetting that whilst improving the lithography process over time has postive consequences over time for reducing the cost of a product there are other factors that people forget.
- The increased cost per wafer for new technology -> I.E $7000 vs $5000 for an older process (TSMC 40nm vs 55nm)
- The process will have lower yields, so more defects per chip initially means higher per chip costs.
- There are other significant costs such as the # of PCB layers, redisigning the chip and royalty charges which must be paid as well. Remember they don't own the I.P to the Cell, RSX or XD ram interface and must therefore pay royalties to use these technologies.
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Hmmm... this is usually true for a very short period of time, but I'm not familiar with going to a reduced process (more chips per die) as producing anything but higher yields very quickly. Please illuminate me. 