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slowmo on 05 April 2009
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Procrastinato said:

SPUs are CPUs. Seriously, if anyone doesn't understand this, and they call themselves a software engineer, they need to go back to school, and they need to do it now.

If you're not a software engineer, I strongly advise you to take the advice of actual software engineers who understand that the SPUs ARE CPUs, in every sense of the word. The SPEs are not capable of addressing main memory directly, and instead address their localstore (something like a L2 cache, but addressable, as I stated), and use 16 DMAs to transfer data in and out. That's it. That's the only real difference, other than the fact that they lack a branch predictor, and have incredible vector math operations and muscle, along with the bazillion registers needed for just that.

Since caching mechanisms are really just a convenient form of fast memory with what amounts to "automatic DMA transfers", the SPUs really just boil down to being full CPUs, without some conveniences -- but lacking those conveniences allows the chips to have WAY more cores. A good tradeoff, if you're willing to work around the conveniences.

Since the automation of the conveniences has never really been very efficient anyway, the hand-crafted code work that goes into making a SPE job also ends up making the SPE jobs brutally efficient.

The hand-crafted performance takes work (and as I said, you can do the same on the 360, if you put the effort in... its a shame all that wasted convenience logic goes unused though, when it could have made for more cores...), but in the end no highly-compiler-dependant, hardware-convenience-reliant chunk of code can ever hope to compare to well-written, well-designed "manual" code.

Can you buy most high-end sportscars with an automatic transmission? Would you want to?  Honestly, if you're into programming, writing an app on the PS3 is fun, because it rewards you well for doing hard work.  Squeezing "75%" of the performance out of the Xenon is easier than squeezing "75%" out of the Cell though.  Getting more is easier, and more fun, on the Cell however, and the end result on the Cell is just plain unmatched (by the Xenon), when it comes down to it -- both will still benefit from the harder effort, though, for certain.

 

(SPU == Synergistic Processing Unit... i.e. the processor+localstore.  SPE == Synergistic Processing Element... i.e the SPU, plus the 16 DMAs/bus interface, basically.)

Did I claim at any point to be a software engineer, I thought it was quite clear I'd heard different to MikeB and hence asked why they were considered CPU's.  It would seem my understanding of the defintion of CPU is different to the general view now which is its another word for processor or microprocessor. 

Perhaps the traditional understanding of what a CPU was in my case makes it hard to understand how it could be labelled as such.  Having done some more reading I think when combined as a package each SPE could be labelled a CPU indeed, what I don't understand is does the SPU actually have a instruction set (RISC) which is what in my terminolgy understanding is actually a element required for a CPU.  I now the SPE has a instruction set so perhaps it would be fairer to say the SPE is a CPU and the SPU a compnent of it.  Regardless I'm wrong questioning the last quote to a degree, but would my statement just now be a more correct defintion or have I just lost the plot (please be gentle).