| drkohler said: Please note that the graph that is shown above is not correct as it "beautifies" the situation for XDR. Currently, XDR ram can be as fast as GDDR5 ram. An actual comparison of both ram architectures is difficult as it depends on many factors (bus width/bus clock/"deepness of the XDR"). The main advantage of XDR is its lower power consumption (and possibly less data/address lines depending on implementation). If you really want to know about cell architecture, go to IBM website (much of what errorrr wrote is more or less incorrect). |
I've said, how cell's detail works I have no idea, but I think there is a reason that XDR was chosen to work with Cell as oppose to GDDR3... XDR is about the same speed as GDDR5, but for the sake of our discussion which is probably comparison to X360's GDDR3, XDR is comparably without a doubt faster GDDR3. And XDR2 is no doubt faster than GDDR5. From what I've read, XDR focuses on low latency, small block transaction as oppose to GDDR3's large block higher latency transaction. If I understand correctly, GDDR3 uses a 4n type pre-fetch, while XDR utilizes a 16n pre-fetch, from that it's pretty clear to see that XDR'interface can handle more transaction than GDDR3's interface. However, I think XDR's fetch are smaller than GDDR3...
And obivously, I don't think many of the average gamer would even comprehend the nitty gritty of XDR for example (Straight from Rambus' site)
* DRSL (Differential Rambus Signaling Level) is a low-voltage, low-power, differential signaling standard that enables the scalable multi-GHz, bi-directional, and point-to-point data busses that connect the XIO cell to XDR DRAM devices. XDR memory solutions also use the Rambus Signaling Level (RSL) standard developed originally for the RDRAM® memory interface, enabling up to 36 devices connected to the source-synchronous, bussed address and command signals.
* ODR (Octal Data Rate) is a technology that transfers eight bits of data on each clock cycle, four times as many as today's state-of-the-art memory technologies that use DDR (Double Data Rate). XDR data rates are scalable to 8.0 GHz.
* FlexPhase deskew circuits eliminate any systematic timing offsets between the bits of an XDR memory interface data bus. With a resolution of 2.5ps (at 3.2 GHz) and a maximum range of over 10 ns, the FlexPhase technology eliminates the need to match trace lengths on the board and package. FlexPhase also dynamically calibrates out on-chip clock skew, driver/receiver mismatch, and clock standing wave effects allowing lower system cost designs.
* Dynamic Point-to-Point (DPP) technology maintains the signal integrity benefits of point-to-point signaling on the data bus while providing the flexibility of capacity expansions with module upgrades. Memory modules can be dynamically reconfigured to support diferrent data bus widths, allowing a memory controller with a fixed data bus width to connect to a variable number of module
Do most people even comprehend these terms? Telling people to read their website is a good advice, if the website can put it in laymen terms lol...
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