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MikeB said:

@ selnor

What I am posting is from a M$ e-mail from their own comparitive analysis


I don't think it's from Microsoft, maybe some anonymous troll sending out fake Spam. Sure Microsoft likes to mislead, but that "email" is far over the top. I won't do a complete runthrough as I already addressed everything here on VGchartz before.

Just one for illustration:

The Cell's seven DSPs (what Sony calls SPEs) have no cache, no direct access to memory, no branch predictor, and a different instruction set from the PS3's main CPU.


Each SPE does have a tiny amount of cache, they all do have DMA units and a branch predictor  is not needed with properly designed SPE code (the programmer does so manually, like shifting gears, but more efficienty than a predictor can).

Why do processors need cache to perform properly? The answer is simply, operating speed, for working on data as fast as possible. One thing you will note when looking at each SPE's memory is that it's the same kind of RAM that is used for cache elsewhere. Just because this memory does share the limitations of cache when used, does not give other CPUs an advantage.

his info certainly doesnt lie and is accurate


You wish... It's inaccurate, incomplete, biased and thus entirely useless.

Your very wrong Mr MikeB. It is from M$. (and I trust their Boffins much more than Sony or you, becuse they have been working with this sort of hardware far longer than Sony or you). It's from IGN where IGN state the following "We decided to put this Microsoft-provided information up undigested. Thus, enclosed is a Microsoft-made comparitive analysis. We have not altered, added, or tinkered with the data. We have not interpreted the specs. We have cut and pasted this information from the email into our site and formatted it."So you can blabber about Cache all you want. Bottom line is I trust them more with this stuff. It's like either listening to Ferrari about performance of cars or Rover about performance of cars. One has been doing it alot longer than the other.