Trumpstyle said:
The github leak clearly says PS5 is 36CU and I think that is fine. Based on all the leaks I think we are looking at: PS5, 300mm2, 36(40)CU, Tsmc 7nm euv and for Xbox series X 350mm2, 52(56)CU also with tsmc 7nm euv. It's very likely that Wccftech and Eurogamer got the die size for Xbox series X wrong. And I don't think 40(44) CU layout is possible based on looking at Navi10 and Navi14. |
The Github leak is not the indication that the final console will be using that setup. It clearly a very old test without context and without any concrete info. many number and data that came are inaccurate and contradicted, also AMD masked their GPU/CPU/APU id and chip ID to confuse data miners.
Even Komachi, Tum Appisak and others data miners has explained that their data are from very old test back from early 2017 early 2018. A lot of thing has change in 2019 to 2020.
Also even if Sony are targeting 9 teraflop it will not work with 2 Ghz of 36 CU. It will burn the chip and super inefficient and will be more expensive then using 52 CU run at lower clock speed to achieved 9 Teraflop.
Another prove is the chip size you mentioned is incorrect, You are using Aquazhi leaker number on comparing Arden (350 mm2) with Oberon (300mm2). Arden actually around 410 mm2 (from Scarlet Engine Phils shows in His Twitter profile). So we still don't know how big PS5 APU is or which APU Sony will be using for.
Even if Aquazhi is correct with 15% different size with Arden and Oberon , Sony APU are still able to fit more CU more then 36 CU. If The Info from Windows Central are true that Arden are using 56 active CU (from total 60 Cu) then with 15% smaller die size on Oberon, Oberon will still able to fit around 52 Cu with 48 Active.
Also alot of trustworthy insider mentioned that both console will be very close in teraflop number and performance , the difference will be on secret sauce and other methode and games exclusives and service.
It's to early to make conclusion.