IBM continues Cell development

[joeorc]

blablubb said:

joeorc said:

jetrii said:

 

me..have no idea what i am taliking about?

that's rich.

the Cell processor is a stream processor, pure and simple that's a fact. gimped core's. god you are just as thick as the "if it's not x86" is crap for game's. that very way of thinking is what stunt's growth in computing.

you have a one track mind my friend just stop. 

while i respect you I do not happen to agree with your take on how and which processor is classed in your IDEA what a stream processor is or is not.

lol, What the hell are you talking about ?

Neither the PS3, nor the XBOX360 or the Wii are x86 compatible, they are all PowerPC based.

The only recent x86 console thats worth mentioning, was the original XBOKS, so i don't think there are many x86 fanatics on this forum.

All this might come as a surprise to you!

p.s.

On Topic:

Regarding your CELL = Stream Processor discussion:

I haven't looked it up on wiki yet, but i'm on jetrii's side.

Why ? Cause he might know the difference between PowerPC and x86.

I know that...

I was talking about his statement that the "SPEs do not make sense anymore and IBM knows this"

that's the same kind of talk that people who want the status quo to remain the same, and keep the x86 alway's in the forefront of alway's being better than powerPC processor's.

an Elitist. if its not a GPU or a x86 than its not good for game's .

AND 

you agree with them is alright and ok but For me I tend to agree with one of the main designer's of what the chip is or is not:

DR. Hofstee explains what the Cell is:

ABSTRACT

 

This paper describes the architecture and implementation of the original gaming-oriented synergistic processor element (SPE) in both 90-nm and 65-nm silicon-on-insulator (SOI) technology and introduces a new SPE implementation targeted for the high-performance computing community. The Cell Broadband Engine^™ processor contains eight SPEs. The dual-issue, four-way single-instruction multiple-data processor is designed to achieve high performance per area and power and is optimized to process streaming data, simulate physical phenomena, and render objects digitally. Most aspects of data movement and instruction flow are controlled by software to improve the performance of the memory system and the core performance density. The SPE was designed as an 11-FO4 (fan-out-of-4-inverter-delay) processor using 20.9 million transistors within 14.8 mm² using the IBM 90-nm SOI low-k process. CMOS (complementary metal-oxide semiconductor) static gates implement the majority of the logic. Dynamic circuits are used in critical areas and occupy 19% of the non-static random access memory (SRAM) area. Instruction set architecture, microarchitecture, and physical implementation are tightly coupled to achieve a compact and power-efficient design. Correct operation has been observed at up to 5.6 GHz and 7.3 GHz, respectively, in 90-nm and 65-nm SOI technology.

http://portal.acm.org/citation.cfm?id=1345059.1345063&coll=GUIDE&dl=GUIDE&CFID=63865659&CFTOKEN=31018906