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Kynes said:
What I'm suggesting is to improve the PPU/SPU ratio, and make PPU out of order, not to improve the SPU functionality. Keep them very specialized, having a low power and transistor budget, to help the PPUs in a GPGPU way. Something similar to what AMD is going to do with Llano, 4 x86 cores, ¿480? stream engines in a die. If you want an heterogeneous architecture, at least it has to be designed to the workload a Joe Sixpack's PC will do.

That architecture does not make sense. The SPEs are stuck at a crossroads. They are not sophisticated enough to be used as general cores, but they are more sophisticated than needed for raw number crushing. IBM knows this, which is why they ended the cell architecture. Instead of XX SPEs, the silicon could be used to make XXXX stream processors which would accomplish the same thing and be faster. 

In fact, that is what IBM is doing. Their next generations of high performance chips will actually be a few Power7/8 cores and several thousand stream processors. The PPE + SPE architecture made sense in 2005, it does not make sense in 2009+.



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