https://wccftech.com/xbox-scarlett-apu-die-shot-analysis-die-size-estimated/

Editor's Warning: Die size estimations are always to be taken with a grain of salt. The slightest distortion/error in perspective correction can result in exponentially large differences. Use of certain lenses can also throw these calculations widely off. These are provided only for fun and to give our readers a "guesstimate" of the actual die size.

 "A picture of the upcoming Xbox Scarlett APU was posted by the 'head of Xbox' Phil Spencer and almost everyone went into a frenzy analyzing the die shot. This is our take and without any further ado, let's begin with the starting image:

The original die shot of the Xbox Scarlett posted by Phil Spencer.

Here is our methodology (A big shout out to WhyCry @Videocardz for helping us with image processing): the original image was enhanced and then perspective corrected (prioritizing the die and not the package). The cleaner parts of the image were then oriented to scale using an older image of the Xbox Scorpio APU, using two different points as an anchor/scale key. The result is a roughly clean image that we can compare on an apples-to-apples basis to get a good idea of the size difference.

A side by side, to-scale (best efforts), comparison of the Scarlett and Scorpio APUs from AMD.

Now assuming Phil did not use a lens with too wonky a perspective (eg: some fisheye lenses), our results show us that the Xbox Scorpio and Xbox Scarlett APUs are roughly the same in width but the Xbox Scarlett APU is slightly longer in height. Our calculations put the Xbox Scarlett APU at roughly 401mm², which is an increase of almost 42mm² over the Xbox Scorpio chip at 359mm². The brand new APU features hardware-based raytracing (which seems to be all the rage these days) and a Zen 2-based CPU core.

Scorpio had 2560 SPs with 2 CUs disabled and while the Xbox Scarlett APU is clearly bigger, it is not possible to speculate based just on the die size because of the different process node involved (7nm vs 16nm) but we can safely say that you are looking at at least 50% more power in the same die space. Since the Scorpio APU can output roughly 6 TFLOPs of power, we can guesstimate a range of at least 9 TFLOPs for the Scarlett APU ( up to 12 TFLOPS is within the realm of possibility).

Interestingly, the chip mentions 8K, as opposed to 4K on Scorpio, which might be an indication of the maximum available resolution on next-generation Xbox consoles. Considering 8K gaming is simply not possible even on a 12 TFLOPs chip (unless you are playing with very rudimentary, low poly models), it is likely that 8K decoding will be supported on the upcoming console. In any case, Xbox will be presenting at AMD's CES Keynote that is going to be happening in a couple of hours so we might find the answer to our question very soon. "

EDIT : Add Digital Foundry Video

Xbox Series X Silicon Revealed: Is This The Biggest Console Processor Ever?

https://youtu.be/v2M01ph1VHM

"It's not possible to speculate based just on die size..."





"but watch us do it anyway"

A rather shallow analysis beyond the die size estimate itself. We do know the size of multiple 7 nm AMD GPUs, APUs and CPUs, for instance, not to mention the size of specific components inside the current consoles' APUs.

It would seem to me, though, that considering the rather large size of the RDNA machinery, not to mention Zen and whatever RT solution AMD has cooked up, it seems troublesome to imagine more than 48 or 52 CUs fitting in there.

I'm thinking more of the Hovis method and vapor chambers instead of a very wide 56 - 64 CU solution as some people have been speculating. And if you think 12 TF is indeed a thing, 48 CUs at ~ 1950 MHz with 4 more disabled would still seem commercially feasible considering even now many custom GPU solutions are required to hit boost clocks around 2000 MHz.

Adored TV takes AMD's wafer allocation for 2020 and guesses approx how many chips and what kind add up to that amount.

18:00 is where he starts talking specifically about the next gen console APU's.

While he's only guessing, and there's a lot to take into account, he get's quite close to the total by the end, so he's likely not far off.

25:00 is where he talks about XBSX specifically. He uses 56 cu's for it's GPU and ends up around 420mm2 for the APU size.

MS are very cocky to show off actual chip designs.

The 40CU PS5 die is rumoured to be around 310-320mm^2. It is unlikely those additional 16-20 CUs would take 90-100mm^2 (assuming a fifth gddr6 controler) in the XSX. It's still a guessing game in the end.

Ya it's all educated guesses, some more than others, but if you follow his logic and reasoning, based on AMD's past, present, and future forecasted sales, along with the more reasonable console spec leaks, it's surprising that adds up so close to AMD's wafer allocation for next year.

It could be completely different than what he thinks, but to be that close without making any wild assumptions, well.

Since we have absolutely no clues about yields (we don't even know on what exact process these thingies will be made), I find it very, let's call it courageous, to argue with wafer allocations.

General info about yields is available for 7nm. They will be made on 7nm or 7nm+, which is what the majority if not all of AMD's silicon will be fabbed on this year. A significant amount has been on 7nm for a while already for Ryzen 3000, Vega VII and Navi 5000.

He takes this into account.

No, that's exactly how much it currently takes for an extra 16 CUs. Take the Radeon 5600 compared to the 5700. 16 extra CUs for exactly 90 - 100 mm2. The CU itself is smaller, but it isn't the only thing you need to add to increase a GPU in size.

Also do consider the PS4 Pro and the XB1X as an example since, despite the die shrink, the RDNA's features in 7 nm take around the same size as GCN on 14 nm. A mere 4 extra CUs on the XB1X for 25 mm2 or so.