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Forums - Microsoft Discussion - Insider Daily. DDR3 RAM inside Xbox One acts like DDR4 from 2014 PCs and really have 272 GB/s BW (Misterxmedia)

fatslob-:O said:

I think you misunderstand what that actually means, it actually means that the CPU cores are cache coherent not the whole cache of the APU which would mean there is no bus between the GPU cache and the cpu cache.

It means the gpu can have cache coherent access to the cpu memory. Notice there is no coherency between esram and cpu, though. Unfortunately there is this small, bidirectional, black arrow between cpu and esram. Nobody has yet figured out what this arrow means. As long as ms doesn't explain what that arrow is, all bets are off about full huma (ms's way of doing it) or not.



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drkohler said:
fatslob-:O said:

I think you misunderstand what that actually means, it actually means that the CPU cores are cache coherent not the whole cache of the APU which would mean there is no bus between the GPU cache and the cpu cache.

It means the gpu can have cache coherent access to the cpu memory. Notice there is no coherency between esram and cpu, though. Unfortunately there is this small, bidirectional, black arrow between cpu and esram. Nobody has yet figured out what this arrow means. As long as ms doesn't explain what that arrow is, all bets are off about full huma (ms's way of doing it) or not.


"It means the gpu can have cache coherent access to the cpu memory." 

this is right but the xbox one doesn't implement any any sort of hUMA system mainly because there is no bus between the GPU cache and CPU cache because I don't see anything from this diagram that says so.

Edit: BTW if your wondering what that arrow actually is, it is probably a way for the CPU to command how the esram will manage memory not a way for the cpu to access esram. Remember when the developers said that they have to manage the esram manually, well it has to be the cpu that controls the esram and not the gpu because it provides more flexibility.



drkohler said:

It means the gpu can have cache coherent access to the cpu memory. Notice there is no coherency between esram and cpu, though. Unfortunately there is this small, bidirectional, black arrow between cpu and esram. Nobody has yet figured out what this arrow means. As long as ms doesn't explain what that arrow is, all bets are off about full huma (ms's way of doing it) or not.

To start to think in hUMA we need to know if the CPU have coherent access to the GPU-cache... the diagram is clear about GPU having access to CPU-cache but what about the reverse?

After that we need to see how this eSRAM works... that black link is intersting but means nothing without more details :(



so confirm X1 really is the more complicated to develop for next gen console



ethomaz said:

drkohler said:

It means the gpu can have cache coherent access to the cpu memory. Notice there is no coherency between esram and cpu, though. Unfortunately there is this small, bidirectional, black arrow between cpu and esram. Nobody has yet figured out what this arrow means. As long as ms doesn't explain what that arrow is, all bets are off about full huma (ms's way of doing it) or not.

To start to think in hUMA we need to know if the CPU have coherent access to the GPU-cache... the diagram is clear about GPU having access to CPU-cache but what about the reverse?

After that we need to see how this eSRAM works... that black link is intersting but means nothing without more details :(


Well to answer your question the reverse has to also be true for the model to work. If you look at the diagram it clearly shows arrows pointing both ways which suggests that the cpu can access gpu cache. Like I said before that black link probably has to do with how the cpu is managing the cache and not using it.

Edit: It would be kinda dumb to not let the cpu have instant access to the results that the GPU computed.  



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fatslob-:O said:

Well to answer your question the reverse has to also be true for the model to work. If you look at the diagram it clearly shows arrows pointing both ways which suggests that the cpu can access gpu cache. Like I said before that black link probably has to do with how the cpu is managing the cache and not using it.

The diagram show you can access in both direction but only highlights the CPU cache coehency but there a lot of chance to you be right... it is more probable.



ethomaz said:

fatslob-:O said:

Well to answer your question the reverse has to also be true for the model to work. If you look at the diagram it clearly shows arrows pointing both ways which suggests that the cpu can access gpu cache. Like I said before that black link probably has to do with how the cpu is managing the cache and not using it.

The diagram show you can access in both direction but only highlights the CPU cache coehency but there a lot of chance to you be right... it is more probable.


The reason they highlighted that the gpu can can access cpu cache has to do with the fact that there are more applications to letting the gpu access the result of what the cpu computed. 





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fatslob-:O said:

Edit: BTW if your wondering what that arrow actually is, it is probably a way for the CPU to command how the esram will manage memory not a way for the cpu to access esram. Remember when the developers said that they have to manage the esram manually, well it has to be the cpu that controls the esram and not the gpu because it provides more flexibility.

I'm pretty sure the gpu is calling the shots, not the cpus, via the host guest gpu mmu. This dark green rectangle is pretty much the core component of the entire SoC as far as data flow is concerned. But it isn't even clear whether the esram is a scratchpad or a cache or something ms-specific. Alos notice the strange black arrow goes bus to bus, not component to component, so it is really a mystery