biglittlesps said:
ninjablade said:
biglittlesps said:
@ninjablade
I did gone through the link you sent and I did update post with link in sources and fabrication process used for Wii GPU, other than that i did not see any changes from that link. I did add these details based on the links i mentioned in the sources. |
did you read it right, there basically saying there is no way its more ten 160sp.
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Yes, I did. They also said it should have 320sp according to die pictures. 160sp/8TMU was just one of their guesses, but Wii U GPU has 320sp/16TMU as i've already did my research based on PC GPU's and architectures of AMD as well to confirm, you can find those details from the links in the sources i added.
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this is a quote from fouth storm a huge nintendo fan and the one that took care of the work to get the gpu die image.
320 SPUs would be a good match for all the data only if we knew for sure that the chip was manufactured on TSMC 40nm, there were 32 register pools in each of the SPU blocks (as in Llano, Brazos, and Trinity), and there existed more than two blocks of TMUs.
At the risk of sounding brash, I can say with 99% certainty that I've correctly identified the TMU blocks in that link I posted. As much as we can say for sure which blocks are the shaders, I believe we can now do this with the TMUs. The more die shots I have compared, the more obvious it seems.
The size of the SPU blocks is the only outlier in our data, really, but I believe function already mentioned that it can be explained when you take into account the different fab house (Renesas vs TSMC). I have attempted to clarify this in the past (although it seems not to have taken hold, unfortunately) that the 40nm TSMC was Jim's guess or a guess from one of his colleagues after taking an initial glance at the die. I followed up with him shortly after on the subject and he said that they had not performed any precise gate measuring, and that 40nm and 55nm were actually pretty hard to tell apart without getting those figures.
I have actually heard through the grapevine that Latte is manufactured on Renesas' 45nm process node. This makes a great deal of sense to me as it seems apparent from the heat spreader labels (which do not mention TSMC) and articles like this one here that the chip is being manufactured by Renesas in-house and is not outsourced. 45nm fits right in with Renesas' current production lines.
To my knowledge, Latte is the first Radeon GPU that Renesas have worked on, and this lack of prior knowledge may have contributed to a less than optimal size for some of the components, which are practically hand-crafted for TSMC's fab lines anyway. Of course, Renesas' engineers have done a bang up job on integrating the eDRAM, something that I doubt TSMC would have been able to pull off. But once you combine this lack of previous experience, larger process node, the possibility of extra transistors here and there to run the BC shim layer, and possibly even just a less dense design target to avoid a RROD situation, I believe we start painting a decent picture as to why those SPU blocks are so large.
